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FUJITSU SEMICONDUCTOR DATA SHEET
Revision 1.0
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89930C Series
MB89P935C/PV930A
I DESCRIPTION
The MB89930C series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as timers, serial interfaces, A/D converter and external interrupts.
I FEATURES
* * * * * * * * * * * * * * * * * MB89600 Series CPU core Minimum execution time: 0.4 s/10MHz Interrupt processing time: 3.6 s/10MHz I/O ports: max. 21 channels 21-bit timebase timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter: 8 channels UART 8-bit serial I/O External interrput 1 (Edge): 3 channels External interrupt 2 (Level): 8 channels Wild Register: 2 bytes OTPROM Read protection (Refer to "I Programming the OTPROM in MB89P935C") Low-power consumption modes (sleep mode and stop mode) DIP and SH-DIP package CMOS Technology
I PACKAGE
32-pin plastic DIP 32-pin plastic SH-DIP
48-pin ceramic MQFP
(DIP-32P-M01)
(DIP-32P-M01)
(MQP-48C-P01)
(DIP-32P-M04)
(DIP-32P-M05)
(MQP-48C-P01)
MB89930C Series
I PRODUCT LINEUP
Part number Parameter Classification MB89P935C One-time PROM product (read protection) 16K x 8-bit (internal PROM) 512 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.4 s to 6.4 s(10 MHz) : 3.6 s to 57.6 s(10 MHz) MB89PV930A Piggyback/evaluation product (for evaluation and development) 32K x 8-bit (external EPROM)
ROM size RAM size CPU functions
Ports 21-bit timebase timer Watchdog timer 8-bit PWM timer
General-purpose I/O ports (CMOS): 21 (also serve as peripherals) (4 ports can be set as N-ch open-drain type) 21-bit Interrupt cycle: 0.82, 3.3, 26.2, or 419.4 ms at 10-MHz main clock Reset generation cycle: 209.7ms minimum at 10-MHz main clock 8-bit interval timer operation (square output capable, operating clock cycle: 1 tinst, 16 tinst, 64 tinst, and 8/16-bit capture timer/counter output) 8-bit resolution PWM operation (conversion cycle: 256 tinst, 4096 tinst, 16384 tinst and 256 times 8/16-bit capture timer/counter output) 8-bit capture timer/counter x 1 channel + 8-bit timer or 16-bit capture timer/counter x 1 channel Capable of event count operation and square wave output using exteranl clock input with 8-bit timer 0 or 16-bit counter Transfer data length: 6/7/8 bits Transfer rate: 300 to 9600 bps at 10 MHz 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 2 tinst, 8 tinst and 32 tinst) Output frequency: Pulse width and cycle selectable 3 channels (interrupt vector, request flag, request output enable) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) 10-bit precision x 8 channels A/D conversion function (Conversion time: 38 tinst) Continuous activation by 8/16-bit timer/counter output or timebase timer counter 8-bit x 2 Sleep mode and Stop mode 3.0V to 5.5V 2.7V to 5.5V
8/16-bit capture timer/counter UART 8-bit Serial I/O 12-bit PPG timer External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) 10-bit A/D converter
Wild Register Standby mode Power supply voltage
Note: 1 Tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock.
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MB89930C Series
I PACKAGE AND CORRESPONDING PRODUCTS
Package MB89P935C MB89PV930A X X
DIP-32P-M04 DIP-32P-M05 MQP-48C-P01
O : Availabe X : Not available
O O
X
O
I DIFFERENCES AMONG PRODUCTS
1. A/D Converter Power Supply Pin (AVCC) and Reference Voltage Input Pin (AVR)
There are AVCC and AVR pins in MB89P935C. They are absent in MB89PV930A. Hence, the electrical characteristics of MB89P935C is different from that of MB89PV930A. (Refer to "I ELECTRICAL CHARACTERISTICS 5. A/D Converter Electrical Characteristics")
2. Curent Consumption
In the case of the MB89PV930A, add the current consumed by the EPROM which is connected to the top socket.
3
MB89930C Series
I PIN ASSIGNMENT
(TOP VIEW)
P04/INT24 P05/INT25 P06/INT26 P07/INT27 MOD0 MOD1 RST X0 X1 Vss P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vcc P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVcc AVR AVss P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI
(DIP-32P-M04) (DIP-32P-M05)
4
MB89930C Series
(TOP VIEW)
P35/INT11 N.C. N.C. N.C. N.C. N.C. Vss N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37
P34/TO/INT10 P33/EC P32/UI/SI P31/UO/SO P30/UCK/SCK P40/AN0 P41/AN1 P42/AN2 P43/AN3 P00/INT20/AN4 P01/INT21/AN5 P02/INT22/AN6
69 70 71 72 73 74 75 76 77 78 79 80 49 50 51 52
60 59 58 57 56 55 54 53
36 35 34 33 32 31 30 29 28 27 26 25
N.C P36/INT12 P37/BZ/PPG X1 X0 RST MOD1 MOD0 P07/INT27 P06/INT26 P05/INT25 P04/INT24
13 14 15 16 17 18 19 20 21 22 23 24
68 67 66 65 64 63 62 61
Pin No. 49 50 51 52 53 54 55 56
Pin Symbol Vpp A12 A7 A6 A5 A4 A3 N.C.
Pin No. 57 58 59 60 61 62 63 64
P03/INT23/AN7 AVss N.C. N.C. N.C. Vcc N.C. N.C. N.C. N.C. N.C. P50/PWM
(MQP-48C-P01)
Pin Symbol N.C. A2 A1 A0 O1 O2 O3 Vss
Pin No. 65 66 67 68 69 70 71 72
Pin Symbol O4 O5 O6 O7 O8 CE A10 N.C.
Pin No. 73 74 75 76 77 78 79 80
Pin Symbol OE N.C. A11 A9 A8 A13 A14 Vcc
N.C.: As connected internally, do not use.
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MB89930C Series
I PIN DESCRIPTION
Pin Number DIP*1 8 9 5 6 MQFP*2 32 33 29 30 Pin Name X0 A X1 MOD0 B MOD1 I/O Circuit Type Function Pins for connecting the crystal resonator for the main clock. To use an external clock, input the signal to X0 and leave X1 open. Memory access mode setting input pins. Connect the pin directly to Vss. Reset I/O pin. The pin is N-ch open-drain type with pullup resistor and a hysteresis input as well. The pin outputs the "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an A/D converter analog input. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O port. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resources is a hysteresis input. General-purpose CMOS I/O port. This pin also serves as the data output pin for the UART or 8-bit serial I/O. General-purpose CMOS I/O port. This pin also serves as the data input pin for the UART or 8-bit serial I/O. The resources is a hysteresis input. General-purpose CMOS I/O port. This pin also serves as the external clock input pin for the 8/16-bit capture timer/counter. The resource is a hysteresis input. General-purpose CMOS I/O port. This pin also serves as the output pin for the 8/16-bit capture timer/counter or as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as the input pins for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O port. This pin also serves as the buzzer output pin or the 12-bit programmable pulse generator output. General-purpose CMOS I/O port. The pin also serves as the 8-bit PWM output pin. General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. The pins also serve as A/D converter analog input pins.
7
31
RST
C
28 to 31
P00/INT20/AN4 to 10 to 13 P03/INT23/AN7
G
1 to 4
25 to 28
P04/INT24 to P07/INT27
D
19
5
P30/UCK/SCK
D
18
4
P31/UO/SO
E
17
3
P32/UI/SI
D
15
2
P33/EC
D
14
1
P34/TO/INT10
D
13,12
48, 35
P35/INT11, P36/INT12
D
11
34
P37/BZ/PPG
E
20
24
P50/PWM P40/AN0 to P43/AN3
E
24 to 27
6 to 9
F
*1: DIP-32P-M04 and DIP-32P-M05 *2: MQP-48C-P01
(Continued)
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MB89930C Series
(Continued)
Pin No. DIP*1 32 10 23 21 22 16 MQFP*2 18 42 -- 14 -- -- Pin Name Vcc Vss AVcc AVss AVR C I/O Circuit Type -- -- -- -- -- -- Power supply pin Power (GND) pin Power supply pin for A/D converter. Power supply pin for A/D converter. Apply equal potential to this pin and the Vss pin. Reference voltage input pin for the A/D converter. Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1F Function
*1: DIP-32P-M04 and DIP-32P-M05 *2: MQP-48C-P01
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MB89930C Series
*External EPROM Socket (MB89PV930A only)
Pin Number MQFP 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 75 76 77 78 79 80 56 57 72 74
*1
Pin Name Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC
I/O O "H" level output pin
Function
O
Address output pins.
I O
Data input pins. Power supply pin (GND).
I
Data input pins.
O O O
Chip enable pin for the ROM. Outputs "H" in standby mode. Address output pin. Output enable pin for the ROM. Always outputs "L".
O
Address output pins.
O
Power supply pin for the EPROM.
N.C.
--
Internally connected pins. Always leave open.
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MB89930C Series
I I/O CIRCUIT TYPE
I/O Circuit Type
X1 Nch X0 Pch Pch Nch
Circuit
Remarks
A
* Crystal oscillation type
Standby control signal
B
* CMOS input
R Pch
C
Nch
* The pull-up resistance (Pchannel) Approx. 50 k. * Hysteresis input
R Pch Pch
D
Nch
* CMOS output * CMOS input * Hysteresis input (Resource input) * Selectable pull-up resistor Approx. 50 k.
R Pch Pch
E
Nch
* CMOS output * CMOS input * Selectable pull-up resistor Approx. 50 k
(Continued) 9
MB89930C Series
(Continued)
Pch open-drain control
F
Nch Analog input
* CMOS output * CMOS input * Analog input * N-ch open-drain output available
A/D enable
R Pch Pch
G
N-ch
* CMOS output * CMOS input * Hysteresis input (Resource input) * Analog input * Selectable pull-up resistor Approx. 50k.
Analog input
A/D enable
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MB89930C Series
I HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in "I Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor of at least 2 kilohms between the pin and the power supply.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Treatment of Power Supply Pins on Microcontrollers with A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wakeup from stop mode.
7. About the Wild Register Function
No wild register can be debugged on the MB89PV930A. For the operation check, test the MB89P935C installed on a target system.
8. Program Execution in RAM
When the MB89PV930A is used, no program can be executed in RAM.
11
MB89930C Series
I PROGRAMMING THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adaptor
To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 Adaptor socket part number ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403 FAX 81-3-5396-9106
3. Memory Space
Memory space in each mode is diagrammed below.
Address 0000H
Normal operating mode I/O
Corresponding addresses on the EPROM programmer
0080H RAM 0880H 8000H Not available 0000H
PROM 32KB
EPROM 32KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
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MB89930C Series
I PROGRAMMING THE OTPROM IN MB89P935C
1. Memory Space
Normal operating mode Address 0000H I/O 0080H
RAM 512Byte
0280H Corresponding addresses on the ROM programmer Address C000H C000H
Not available
PROM 16KByte
PROM 16KByte
FFFFH
FFFFH
2. Programming the OTPROM
* To program the OTPROM using EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer Corp.). Inquiry : Yokogawa Digital Computer Corp. : TEL (81)-42-333-6224 * To program the OTPROM using FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220 Note : Programming the OTPROM in MB89P935C is serial programming mode only.
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MB89930C Series
3. Programming Adaptor for OTPROM
* To program the OTPROM using EPROM programmer AF200, use the programming adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below.
Package DIP-32P-M04 DIP-32P-M05
Adaptor socket part number ROM3-FPT30M02-8LA-FJ Not available
Inquiry : Sun Hayato Co., Ltd : TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 * To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adaptor listed below.
Package DIP-32P-M04 DIP-32P-M05
Adaptor socket part number MB91919-809 + MB91919-800 MB91919-814 + MB91919-800
Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220
4. OTPROM Content Protection
OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by any serial programmer. Note : The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H" in FFFCH). It is advised to write the OTPROM protection code at last.
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MB89930C Series
I Block Diagram
X0 X1
Oscillator circuit Clock control
Timebase timer
CMOS I/O port 8bit PWM Port 5
P50/PWM
RST
Reset circuit CMOS I/O port UART prescaler Switching serial function
Port 0
P04/ INT24 P07/ INT27 P00/ INT20 /AN4 P03/ INT23 /AN7
4
8
External interrupt 2 (wake-up) Internal data bus
UART
4
4
P30/UCK/SCK P31/UO/SO P32/UI/SI
AVcc AVss AVR
P40/AN0 P43/AN3
4
Port 4
4
Port 3
10-bit A/D converter
8-bit serial I/O
8/16-bit capture timer/counter
External interrupt 1 (wake-up)
P33/EC P34/TO/INT10
CMOS I/O port (Nch-OD)
3
2
P35/INT11 P36/INT12
512-byte RAM
F2MC-8L CPU 16-KB ROM Other pins Vcc,Vss,MOD1,MOD0,C Wild register
12bit PPG
P37/BZ/PPG
Buzzer output CMOS I/O port
15
MB89930C Series
I CPU CORE
1. Memory Space
The microcontrollers of the MB89930C series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89930C series is structured as illustrated below.
Memory Space
MB89P935C 0000H I/O 0080H RAM 512B 0100H 0200H 0280H
Generalpurpose registers
MB89PV930A 0000H I/O 0080H RAM 512B 0100H 0200H 0280H
Generalpurpose registers
Not available 8000H C000H
Not available
External EPROM PROM 16KB 32KB
FFFFH
FFFFH
16
MB89930C Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
RP 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 CCR 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
CCR initial value X011XXXXB
X : Undefined
H-flag I-flag IL1,0 N-flag Z-flag V-flag C-flag
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MB89930C Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
18
MB89930C Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89930C series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
19
MB89930C Series
I I/O MAP
Address 00H 01H 02H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH SMC SRC SSD CNTR COMR EIC1 EIC2 PWM control register PWM compare register External interrupt 1 control register 1 External interrupt 1 control register 2 (Reserved) Serial mode control register Serial rate control register Serial status and data register R/W R/W R/W 00000-00B --011000B 00100-1XB (Continued) 20 PDR3 DDR3 RSFR PDR4 DDR4 OUT4 PDR5 DDR5 RCR21 RCR22 RCR23 RCR24 BZCR TCCR TCR1 TCR0 TDR1 TDR0 TCPH TCPL TCR2 Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 4 direction register Port 4 output format register Port 5 data register Port 5 data direction register 12-bit PPG control register 1 12-bit PPG control register 2 12-bit PPG control register 3 12-bit PPG control register 4 Buzzer register Capture control register Timer 1 control register Timer 0 control register Timer 1 data register Timer 0 data register Capture data register H Capture data register L Timer output control register (Reserved) R/W W R/W R/W 0-000000B XXXXXXXXB 00000000B ----0000B SYCC STBC WDTC TBTC Standby control register Watchdog timer control register Timebase timer control register (Reserved) R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W XXXXXXXXB 00000000B XXXX----B ----XXXXB ----0000B ----0000B -------XB -------0B 00000000B --000000B 0-000000B --000000B -----000B 00000000B 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ------00B Register name PDR0 DDR0 Register Description Port 0 data register Port 0 data direction register (Reserved) System clock control register R/W R/W W R/W 1--11100B 00010---B 0---XXXXB 00---000B Read/Write R/W W Initial value XXXXXXXXB 00000000B
MB89930C Series
(Continued) Address 2BH 2CH 2DH to 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH to 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48 to 6FH 70H 71H 72H 73H to 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 ITR PUL0 PUL3 PUL5 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WREN WROR SMR SDR SSEL Serial mode register Serial data register Serial function switching register (Reserved) Upper-address setting register 1 Lower-address setting register 1 Data setting register 1 Upper-address setting register 2 Lower-address setting register 2 Data setting register 2 Wild-register enable register Wild-register data test register (Reserved) Port 0 pull-up setting register Port 3 pull-up setting register Port 5 pull up setting register (Reserved) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt test register W W W W Not available 11111111B 11111111B 11111111B 11111111B ------00B R/W R/W R/W 00000000B 00000000B -------0B R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXX00B ------00B EIE2 EIF2 ADC1 ADC2 ADDH ADDL ADEN Register name SIDR SODR UPC Register Description Serial input data register Serial output data register Clock division selection register (Reserved) A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L A/D enable register (Reserved) External interrupt 2 control register1 External interrupt 2 control register 2 (Reserved) R/W R/W R/W 00000000B XXXXXXXXB -------0B R/W R/W 00000000B -------0B R/W R/W R/W R/W R/W -0000000B -0000001B ------XXB XXXXXXXXB 00000000B Read/Write R W R/W Initial value XXXXXXXXB 11111111B ----0010B
- : Unused, X : Undefined Note : Do not use reserved area.
21
MB89930C Series
I ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Power supply voltage A/D converter reference input voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "H" level maximum output current "H" level average output current "H" level total maximum output current Power consumption Operating temperature Storage temperature Symbol VCC AVCC AVR VI VO IOL1 IOL2 IOLAV Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 6.0 20 10 4 100 -10 -2 -50 200 +85 +150 Unit V V V V mA mA mA mA mA mA mA mW Average value (operating current x operating rate) Pins P40 to P43 Pin excluding P40 to P43 Average value (operating current x operating rate) Remarks AVCC must not exceed VCC AVR must not exceed AVcc

-40 -55
IOL
IOH IOHAV
IOH
PD TA Tstg
C C
WARNING: Semiconductor device can be permanently damaged by application of stress (voltage, current, temperature etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
22
MB89930C Series
2. Recommended Operating Conditions
Parameter Symbol VCC AVCC AVR VIH "H" level input voltage VIHS VIL "L" level input voltage VILS Open-drain output pin application voltage VD VSS - 0.3 VSS - 0.3 0.2 VCC VCC + 0.3 V V 0.8 VCC VSS - 0.3 VCC + 0.3 0.3 VCC V V Value Min. 3.0* 1.5 4.5 0.7 VCC Max. 5.5 5.5 AVCC VCC + 0.3 Unit V V V V P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P40 to P43
(AVss = Vss = 0.0 V)
Remarks Operation assurance range Retains the RAM state in stop mode
Power supply voltage A/D converter reference input voltage
Operating temperature TA -40 +85 C *: This value depend on the operating conditions and the analog assurance range. See Figure 1 and "5. A/D converter Electrical Characteristics."
23
MB89930C Series
5.5 5.0 4.5 Operating Voltage (V)
Analog accuracy assurance range
4.0
Operation assurance range
3.5 3.0 2.5 2.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Operating Freq. (MHz)
Figure 1
Operating Voltage vs. Operating Frequency
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
24
MB89930C Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHZ(External clock), TA = -40C to +85C)
Parameter Symbol Pin P00 ~ P07, P30 ~ P37, P40 ~ P43, P50, UI/SI RST, MOD0/1, UCK/SCK, EC, INT20 ~ INT27, INT10 ~ INT12 P00 ~ P07 P30 ~ P37, P40 ~ P43, P50, UI/SI RST, MOD0/1, UCK/SCK, EC, INT20 ~ INT27, INT10 ~ INT12 Condition Value Min. 0.7 VCC Typ. -- Max. VCC + 0.3 Unit Remarks
VIH "H" level input voltage VIHS
--
V
--
0.8 VCC
--
VCC + 0.3
V
VIL "L" level input voltage VILS
--
VSS - 0.3
--
0.3 VCC
V
--
VSS - 0.3
--
0.2 VCC
V
Open-drain output pin application voltage
VD
P40 ~ P43
--
VSS - 0.3
--
VCC + 0.3
V
"H" level VOH output voltage VOL1 "L" level output voltage VOL2 Input leakage current Pull-up resistance ILI
P00 ~ P07, P30 ~ P37, IOH = -4.0mA P40 ~ P43, P50 P00 ~ P07, P30 ~ P37, IOL = 4.0 mA P50, RST P40 ~ P43 IOL = 12.0 mA
2.4 -- -- --
-- -- -- --
-- 0.4 0.4 +5
V V V A k Without pullup resistor
P00 ~ P07, P30 ~ P37, 0.45 V < VI < P40 ~ P43, P50, VCC MOD0/1 P00 ~ P07, P30 ~ P37, VI = 0.0V P40 ~ P43, P50 FCH = 10.0MHz Tinst= 0.4s Main clock run mode VCC (External clock
RPULL
25
50
100
ICC
--
6
9
mA
ICCS Power supply current ICCH IA
operation)
FCH = 10.0MHz Tinst= 0.4s Main clock sleep mode Stop mode Ta=+250C When A/D converting
--
3
5
mA
-- --
-- 2.3
10 6
A mA A pF
AVcc IAH Input capacitance Other than AVCC, AVSS, AVR, VCC, VSS
When A/D stops Ta=+250C --
--
--
5
CIN
--
10
--
25
MB89930C Series
4. AC Characteristics
(1) Reset Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter RST "L" pulse width Symbol tZLZH Condition -- Value Min. 48 tHCYL* Max. -- Unit ns Remarks
* : tHCYL is the oscillation cycle (1/FC) to input to the X0 pin.
tZLZH RST
0.2 VCC
0.2 VCC
Note: The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH. (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition -- Value Min. -- 1 Max. 50 -- Unit ms ms Due to repeated operations Remarks
tR 2.0 V 0.2 V
tOFF
VCC
0.2 V
0.2 V
Note: The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation setting time.
26
MB89930C Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH tHCYL tWH tWL tCR tCF -- Condition
Value
Min. 1 100 20 -- Max. 10 1000 -- 10
Unit MHz ns ns ns
Remarks
X0 and X1 Timing and Conditions
tHCYL tWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF tWL
Main Clock Conditions
When a crystal or ceramic reasonator is used When an external clock is used
X0
X1 FCH
X0
X1 Open
FCH
(4) Instruction Cycle
Parameter Instruction cycle (minimum execution time)
Symbol tinst
Value 4/FCH, 8/FCH, 16/FCH, 64/FCH
Unit
Remarks tinst = 0.4 s when operating at FCH = 10 MHz (4/FCH)
s
27
MB89930C Series
(5) Peripheral Input Timing
(AVCC = VCC = 5.0 V + 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width
Symbol tILIH tIHIL
Pin INT10 ~ INT12, INT20 ~ INT27, EC
Value Min. 2 tinst* 2 tinst* Max. -- --
Unit
Remarks
s s
* : For information on tinst, see "(4) Instruction Cycle."
INT10 ~ INT12, INT20 ~ INT27, EC
tIHIL
tILIH
0.8 Vcc
0.8 Vcc
0.2 Vcc
0.2 Vcc
(AVCC = VCC = 5.0 V + 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" noise limit Peripheral input "L" noise limit
Symbol tIHNC tILNC
Pin INT10 to INT12, EC
Value Min. 7 7 Typ. 15 15 Max. 23 23
Unit ns ns
Remarks
* : For information on tinst, see "(4) Instruction Cycle."
INT10 ~ INT12, EC
tILNC
tIHNC
0.8 Vcc
0.8 Vcc
0.2 Vcc
0.2 Vcc
28
MB89930C Series
(6) UART, Serial I/O Timing (AVCC = VCC = 5.0 V, AVSS = VSS= 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time UCK/SCK SO time Valid SI UCK/SCK UCK/SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK/SCK SO time Valid SI UCK/SCK UCK/SCK valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI UCK/SCK UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI External shift clock mode Internal shift clock mode Condition Value Min. 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max. -- 200 -- -- -- -- 200 -- -- Unit
s
ns
s s s s
ns
s s
* : For information on tinst, see "(4) Instruction Cycle."
Internal Shift Clock Mode
tSCYC 2.4 V
UCK/SCK
0.8 V
tSLOV 2.4 V
0.8 V
SO
0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX
0.8 VCC 0.2 VCC
External Shift Clock Mode
tSLSH 0.8 VCC tSHSL 0.8 VCC
UCK/SCK
0.2 VCC
tSLOV 0.2 VCC
SO
2.4 V 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX
0.8 VCC 0.2 VCC
29
MB89930C Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics AVCC = VCC = 5.0 V +10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Total error -- Symbol Pin Value Min. -- -- Typ. 10 -- Max. -- +3.0 +5.0 +2.5 +3.0 +1.9 +2.5 Unit bit LSB MB89P935C MB89PV930A MB89P935C MB89PV930A MB89P935C MB89PV930A MB89P935C MB89PV930A MB89P935C MB89PV930A Remarks
Linearity error
--
--
LSB
Differential linearity error
--
--
--
LSB
Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current
VOT
AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB AVSS - 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB AVR - 3.5 LSB AVR - 1.5 LSB AVR + 0.5 LSB AVR - 6.5 LSB AVR - 1.5 LSB AVR + 2.0 LSB -- -- -- -- -- 140 -- 38 tinst* 10 AVR AVCC 260 5
LSB
VFST
LSB s A V V A A
IAIN VAIN -- IR IRH
AN0 to AN7
-- AVSS AVSS + 3.0
AVR
-- --
At A/D start At A/D stop
* For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics." (2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics. * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. * Total error (unit: LSB) The difference between theoretical and actual conversion values.
30
MB89930C Series
Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD
Total error
Actual conversion value
{1 LSB x N + VOT}
Digital output
004 003 002 001 0.5 LSB AVSS Analog input AVCC
Digital output
004 003
VNT Actual conversion value Theoretical value
VOT 1 LSB
002 001 AVSS
AVCC Analog input
1 LSB =
VFST - VOT 1022
(V)
Total error = VNT - {1 LSB x N + 0.5 LSB} 1 LSB
Full-scale transition error
Zero transition error 004 Actual conversion value 003 3FF
Theoretical value
Actual conversion value
Digital output
Digital output
3FE VFST (Actual measurement) Actual conversion value 3FC AVCC
002 Actual conversion value 001
3FD
VOT (Actual measurement) AVSS Analog input
Analog input
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x N + VOT} VFST (Actual measurement) N+1
Differential linearity error
Theoretical value
Actual conversion value
V(N + 1)T
Digital output
Digital output
N
VNT
004 003 002 001 AVSS Analog input Theoretical value
N-1 Actual conversion value
VNT Actual conversion value
N-2 AVCC Analog input
VOT (Actual measurement) AVCC AVSS
Linearity error =
VNT - {1 LSB x N + VOT} 1 LSB
Differential linearity error =
V(N + 1)T - VNT 1 LSB
-1
31
MB89930C Series
(3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89930C series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 4k). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin.
Analog Input Circuit Model
Analog input pin
Sample hold circuit
Comparator
If the analog input impedance is higher than 4 k, it is recommended to connect an external capacitor of approx. 0.1 F.
R
C
Close for 16 instruction cycles after activating A/D conversion. Analog channel selector
* Error The smaller the |AVR - AVSS|, the greater the error would become relatively.
32
MB89930C Series
I EXAMPLE CHARACTERISTICS
* Power Supply Current (External Clock)
MB89P935A At The Main Clock Operation (Highest Clock Gear)
Icc vs. Vcc
Icc (mA) 3.5 TA = +25 C 3 Fc = 10MHz 2.5 Fc = 8MHz 2 1.5 1 0.5 0 2 3 4 5 6 7 Vcc (V) Fc = 4MHz Iccs (mA) 1.6 1.4 1.2 1
MB89P935A At The Main Sleep Operation (Highest Clock Gear)
Iccs vs. Vcc
Fc = 10MHz Fc = 8MHz
TA = +25 C
Fc = 4MHz 0.8 0.6 0.4 0.2 0 2 3 4 5 6 7 Vcc (V)
33
MB89930C Series
I INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols
Symbol
dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits)
Meaning
Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) (Continued)
34
MB89930C Series
(Continued)
Symbol
EP PC SP PS dr CCR RP Ri Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits)
Meaning
Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
x
(x) (( x ))
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following:
* "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00.
N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
35
MB89930C Series
Table 4
Table 2 Transfer Instructions (48 instructions) Mnemonic
MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC
~
3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2
#
2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1
Operation
(dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC)
TL
- - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - -
TH
- - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - -
AH
- - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH
NZVC
---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6
D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
36
MB89930C Series
Table 5
Table 3 Arithmetic Operation Instructions (62 instructions) Mnemonic
ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir
~
3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3
#
1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2
Operation
(A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA
TL
- - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - -
TH
- - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - -
AH
- - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - -
NZVC
++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R-
OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued)
C A
(A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir)
37
MB89930C Series
(Continued)
Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP
~
3 4 3 2 2 3 3 4 3 5 4 5 4 3 3
#
1 2 1 1 2 2 1 2 1 3 2 3 2 1 1
Operation
(A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1
Table 1
TL
- - - - - - - - - - - - - - -
TH
- - - - - - - - - - - - - - -
AH
- - - - - - - - - - - - - - -
NZVC
++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ----
OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Table 1 Branch Instructions (17 instructions)
Mnemonic
BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI
~
3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6
#
2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1
Operation
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt
Table 1
TL
- - - - - - - - - - - - - - - - -
TH
- - - - - - - - - - - - - - - - -
AH
- - - - - - - - - - - - - - dH - -
NZVC
---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore
OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Table 1 Other Instructions (9 instructions) Mnemonic
PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~
4 4 4 4 1 1 1 1 1
#
1 1 1 1 1 1 1 1 1
Operation
TL
- - - - - - - - -
TH
- - - - - - - - -
AH
- dH - - - - - - -
NZVC
---- ---- ---- ---- ---- ---R ---S ---- ----
OP code 40 50 41 51 00 81 91 80 90
38
L
PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC
H
3 4 5 6 7 8 9 A B C D E F
0
1
2
0
NOP
SWAP
RET
RETI
1
MULU
DIVU
A XCH A A, T A A A XOR AND OR
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP
2
ROLC
CMP
ADDC
SUBC
A
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
I INSTRUCTION MAP
3 A DAS
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8
A
ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A
MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP MOV @IX +d,A XOR AND @A,IX A,@IX +d +d OR A,@IX +d MOV CMP CLRB BBC MOVW MOVW MOVW XCHW @IX @IX dir: 6 dir: 6,rel A,@IX @IX IX,#d16 A,IX +d,#d8 +d,#d8 +d +d,A
6
MOV A,@IX +d
CMP A,@IX +d
ADDC A,@IX +d
SUBC A,@IX +d
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3 CALLV BNZ #4 CALLV BZ #5
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MB89930C Series
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
39
MB89930C Series
I ORDERING INFORMATION
Part number
MB89P935CP MB89P935CP-G-SH MB89PV930ACF
Package
32-pin Plastic DIP (DIP-32P-M04) 32-pin Plastic SH-DIP (DIP-32P-M05) 48-pin Ceramic MQFP (MQP-48C-P01)
Remarks
40
MB89930C Series
I PACKAGE DIMENSIONS
32-pin Plastic DIP DIP-32P-M04
41.910.127 (1.650.005)
13.970.127 (.550.005)
2.159.127 (.085.005) 4.5720.254 (.18.01) 3.30(.130) 0.6350.127 (.025.005) 0.254(.010) TYP 0.457(.018) TYP 1.9050.127 (.075.005) 1.27(.050) TYP 2.54(.100) TYP 15.24(.600) TYP 1.842.127 (.0725.005)
C
2001 FUJITSU LIMITED
Dimensions in mm (inches)
32-pin Plastic SH-DIP DIP-32P-M05
28.030.10 (1.104.004)
15 MAX
8.900.15 (.350.006)
10.16 (.400)
11.20.3 (.441.012)
0.270.05 (.011.002) 4.70.15 (.185.006)
3.30.20 (.130.008)
1.778 (.0700)
1.00 (.039)
0.45 (.018)
0.73 (.029)
C
2002 FUJITSU LIMITED D32017Sc-1-1
Dimensions in mm (inches)
41
MB89930C Series
48-pin Ceramic MQFP MQP-48C-P01
(MQP-48C-P01)
Dimensions in mm (inches)
42
MB89930C Series
MEMO
43
MB89930C Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.

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